The present invention relates to methods for transferring thin layers from a wafer to a receiving substrate, to form structures such as a semiconductor-on-insulator (SOI) structures.
The goal of transferring thin layers is typically to produce electronic structures having an active layer, which is the layer that includes or will include the electronic components, that is thin and homogeneous throughout its thickness. A second goal is to produce such structures by transferring the active layer onto a receiving substrate from a wafer having a buffer layer. Such a process may provide the possibility of reusing part of the wafer, in particular at least part of the buffer layer, for another transfer process.
The term “buffer layer” means a layer having a different lattice parameter than that of adjacent layers. The buffer layer is generally an intermediate layer between two crystallographic structures with different lattice parameters. The buffer layer has in the region of one of its faces a lattice parameter that is substantially identical to that of the first structure, and in the region of its other face a lattice parameter that is substantially identical to that of the second structure. For example, a wafer may include a single-crystal silicon (also called Si) wafer and a relaxed layer of silicon-germanium (SiGe) with a buffer layer therebetween, which permits forming the SiGe layer on the Si wafer despite the difference in lattice parameter of these two materials.
A “relaxed layer” is a layer of semiconductor material having a crystallographic relaxation rate, as measured by X-ray diffraction or Raman spectroscopy, in excess of 50%. A layer with a 100% relaxation rate has a lattice parameter substantially identical to the nominal lattice parameter of the material of the layer, and thus the lattice parameter of a material in bulk form is in equilibrium.
Conversely, the term “strained layer” means any layer of a semiconductor material whose crystallographic structure is strained by being in tension or in compression during crystal growth, such as during epitaxial growth. This requires at least one lattice parameter of the layer to be substantially different from the nominal lattice parameter of the material.
A buffer layer makes it possible to grow a SiGe layer on a Si substrate without the SiGe layer being strained by the Si substrate. Given that bulk SiGe is usually not available on the market, the use of a buffer layer of a wafer to obtain a relaxed SiGe layer on the surface makes it possible to produce a structure which can satisfy the same functions as a bulk SiGe substrate. The buffer layer that is inserted between the Si wafer and the relaxed SiGe layer is generally made of SiGe, having a quantity of germanium which progressively increases through the thickness of the wafer towards the relaxed layer. Thus, a silicon-germanium buffer layer can be referred as a Si1-xGex buffer layer, the x parameter representing the germanium concentration in the buffer layer increasing progressively from 0 to r. The relaxed SiGe layer on the surface of the Si1-xGex buffer layer is thus referred as the relaxed Si1-xGex layer, wherein the r parameter represents the germanium concentration in the relaxed layer.
Thus, the Si1-xGex buffer layer makes it possible to gradually increase the germanium content x from the wafer (x=0) towards the relaxed layer (x=r), and to confine defects associated with the difference in lattice parameter so that they are buried. In addition, the Si1-xGex buffer layer makes it possible to give a sufficiently thick relaxed Si1-rGer layer stability with respect to a film of different material epitaxially grown on its surface to strain the latter to modify its lattice parameter without influencing that of the relaxed Si1-rGer layer. For all of these reasons, the buffer layer must be sufficiently thick and typically has a value greater than one micron. Controlling the germanium concentration within a relaxed SiGe layer makes it possible to control its lattice parameter and thus to control the strain exerted on a film that is epitaxially grown on the relaxed SiGe layer.
Processes for transferring a layer of relaxed material that is epitaxially grown on such a buffer layer from the wafer on to a receiving substrate are known. Such processes are, for example, proposed in an IBM document by L. J. Huang et at. “SiGe-On-Insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors”, Applied Physics Letters, Feb. 26, 2001, Vol. 78, No. 9) and in U.S. Pat. No. 5,906,95 1. In these publications, a Silicon-Germanium-On-Insulator (SGOI) structure is produced from a wafer that includes in succession a single-crystal Si support substrate, a SiGe buffer layer and a relaxed SiGe layer.
Another process described in a document by L. J. Huang et at. consists of carrying out a SMART-CUT® process, known to those skilled in the art, to remove the relaxed SiGe layer so as to transfer it by bonding to an oxidized receiving substrate to produce a SGOI structure. Descriptions of the SMART-CUT® process can be found in a number of works concerning wafer reduction techniques. Despite the advantages that this process affords, a few rough areas may formed on the surface of the transferred layer and thus a surface finishing step would then have to be conducted. The finishing step is generally carried out by using CMP (chemical-mechanical polishing or chemical-mechanical planarization), which may create surface defects (such as strain-hardened regions). Using CMP may not correct the thickness perfectly, and thus an inhomogeneous layer thickness may be retained that may impede the transfer of the SiGe layer, and thus increase costs.
The process presented in U.S. Pat. No. 5,906,951 includes, in addition to a CMP polishing step, preliminary lapping, polishing and etching steps in order to remove part of the wafer. These steps slow down the overall removal process and increase costs even further, and do not ensure good layer thickness homogeneity. The first goal for using a transfer process mentioned above is therefore not adequately achieved.
In an attempt to alleviate the problem, U.S. Pat. Nos. 5,882,987 and 6,323,108 disclose an overall process for producing SOI (silicon-on-insulator) structures from a wafer that includes in succession a single-crystal Si support substrate, an SiGe layer and an epitaxially grown Si layer bonded to an oxidized receiving substrate. The SMART-CUT® technique is employed and, after bonding the wafer to a receiving substrate, part of the wafer is detached at the Si support substrate. A structure that consists in succession of part of the Si support substrate, the SiGe layer and the epitaxially grown Si layer is thus removed, and the whole assembly is bonded to the oxidized receiving substrate. Two successive selective etching operations are then conducted on the structure. The first removes the remaining part of the Si support substrate with an etching solution such that the SiGe layer forms a stop layer, and the second removes the SiGe layer with an etching solution such that the Si layer forms a stop layer. The resulting structure is an SOI structure with a Si surface layer.
Thus, an SeOI structure is obtained with a semiconductor layer which is both thin and uniform throughout its thickness, substantially identical to the epitaxially grown initial layer, and the process avoids using a finishing step other than a selective etching operation. However, the SiGe layer inserted between the Si wafer and the epitaxially grown Si layer has a typical thickness of between 0.01 and 0.2 microns. This thickness is insufficient, as mentioned above, to fulfill the role of a buffer layer between the Si wafer and a relaxed layer of a different semiconductor material, such as a relaxed SiGe layer. The wafer therefore does not include a buffer layer, and therefore the second goal mentioned above concerning the transfer process is not achieved. In addition, given the order of magnitude of the thickness of the inserted SiGe layer, the state of the resulting structure does not seem defined with certainty.
Another main objective of the transfer relates to producing a final structure including one or more layers in substantially controlled structural states, such as a substantially relaxed SiGe layer. This objective does not seem to be guaranteed by the structure production process described in the document U.S. Pat. No. 6,323,108. PCT Application No. WO 01/99169 provides processes for producing, from a wafer consisting successively of an Si substrate, an SiGe buffer layer, a relaxed SiGe layer and optionally a strained Si or SiGe layer, a final structure with the relaxed SiGe layer on the optional other strained Si or SiGe layer. The technique employed for producing such a structure involves, after bonding the wafer to a receiving substrate, removal of the undesired material of the wafer, by selectively etching the Si substrate and the SiGe buffer layer. Although this technique does make it possible to achieve particularly small layer thicknesses that are homogeneous throughout the layer thickness, it entails destroying the Si substrate and the SiGe buffer layer by chemical etching. These processes therefore do not allow reuse of part of the wafer, and especially at least part of the buffer layer, for further transfers of layers. Thus, the third objective of using a transfer process of obtaining a reusable wafer portion is not achieved.
PCT Application No. WO 02/15244 describes a source wafer, provided before transfer, that includes a relaxed SiGe layer, a strained Si/SiGe layer, a buffer SiGe layer, and a Si substrate structure. A SMART-CUT® process is used at the strained Si layer level to conduct the transfer. But implanting ions in the strained layer of Si can be difficult due to the thickness of such a layer, and can thus lead to creating structural damage in the SiGe layers surrounding it.
Thus, improvements in achieving these objectives are desired and these are now provided by the present invention.